An example of a process of forming a device isolation layer is a shallow trench isolation (STI) process. The STI process includes etching a semiconductor substrate to form a trench, filling the trench with an insulating layer, and planarizing the insulating layer to fill the trench. As semiconductor devices become increasingly integrated, the aspect ratio of a trench can increase. As the aspect ratio of the trench increases, it can be difficult to fill the trench with an insulating layer. For example, in the case of flash memory devices, it can be difficult to fill the trench having a high aspect ratio only with a high density plasma (HDP) layer or an undoped silicate glass (USG) layer. To address this difficulty, a hybrid gap-fill structure having multiple layers including a spin-on glass (SOG) layer and the HDP layer has been introduced. However, the complexity of the hybrid gap-fill structure can increase cost.
In the meantime, semiconductor devices are often required to be highly integrated to meet users' demand for excellent performance at a low price. For this, a semiconductor device having a multilayer structure, for example, a flash memory device having a multilayer structure, has been introduced. The flash memory device having a multilayer structure may include a semiconductor substrate, a device isolation layer on the semiconductor substrate to define an active region, a tunnel-oxide layer on the active region, a floating gate electrode, a gate interlayer insulating layer, a control gate electrode, a top semiconductor layer, and a device isolation layer on the top semiconductor layer to define an active region. A process of forming a trench device isolation layer is performed to form a device isolation layer in the top semiconductor layer. In the process of forming a trench device isolation layer, the USG layer or the SOG layer may be used to fill a trench having a high aspect ratio. In the case of using the USG layer or the SOG layer, the process of forming a trench device isolation layer may include an annealing process at a high temperature. The annealing process at a high temperature may affect a tunnel oxide layer previously formed on the bottom portion of the top semiconductor layer. For example, the quality of the tunnel oxide layer may be degraded due to hot temperature stress (HTS). Thus, it can be difficult to apply the process of forming a trench device isolation layer to a semiconductor device having a multilayer structure. Moreover, since the process of forming a trench device isolation layer may include a number of processes, devices formed under the top semiconductor layer may be degraded.